Staff Engineer – Synthesized Model IP Design

About the role

Staff Engineer – Synthesized Model IP Design at Qualcomm. Lead the design and development of synthesizable IP models for emulation and FPGA prototyping platforms.

What you'll do

• Lead the design and development of synthesizable IP models for emulation and FPGA prototyping platforms
• Contribute to architecture and micro-architecture definition, design reviews, and implementation strategies
• Develop and optimize RTL implementations using Verilog/SystemVerilog with focus on functionality, performance, area, and timing closure
• Develop and maintain C/C++ reference models and ensure alignment with RTL implementations
• Drive IP integration, debug, validation, and bring-up activities across simulation, emulation, and FPGA environments

What you need

• 10–18 yrs of experience
• FPGA
• Verilog
• C++
• C
• Python
• Prototyping
• B.Tech or B.E. or B.Sc or BCA or M.Sc or M.Tech or MCA

Good to have

• CI/CD
• Git
• Perl