Staff Physical Design Engineer

About the role

The Staff Physical Design Engineer is role which combines deep hands-on implementation expertise with technical leadership. This role owns complex block- and/or top-level physical design for advanced-node SoCs and leads a small group of engineers to achieve high-quality, on-time delivery.

What you'll do

• Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing
• Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets
• Define and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs
• Perform in-depth analysis and debug of tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions
• Develop, maintain, and enhance physical design methodologies, scripts, and flows (e.g., for PDN, PG, clock structure, exception handling, signoff automation)

What you need

• 8–12 yrs of experience
• VLSI
• Verilog
• Any graduate