Staff/ Senior Staff Engineer, STA

About the role

We are looking for a highly motivated STA Engineer to join our VLSI design team. The ideal candidate will be responsible for driving timing closure and signoff readiness for block-level and full-chip designs across all operating modes and process corners.

What you'll do

• Perform block-level and full-chip Static Timing Analysis (STA) across all modes and corners in MMMC environments
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations
• Develop, validate, and maintain timing constraints, including SDC creation, review, and signoff readiness
• Partner closely with RTL Design, Synthesis, CTS, Physical Design, and Signoff teams to achieve timing closure goals
• Drive timing closure through ECO implementation, timing optimization, and timing convergence activities

What you need

• 7–13 yrs of experience
• VLSI
• Python
• Perl
• Verilog
• B.Tech or B.E. or M.Tech