Staff/ Sr Staff/Principal Engineer, STA

About the role

We are seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis . You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area.

What you'll do

• Physical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists
• Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout congestion and achieve PPA targets
• Conduct flat and hierarchical synthesis, ensuring seamless interface timing budgets
• Manage formal verification (LEC) to ensure logical equivalence between RTL and netlist
• UPF management for multiply power domains

What you need

• 8–15 yrs of experience
• VLSI
• Python
• Verilog
• Perl
• B.Tech or B.E. or M.Tech