Design Verification Architect

About the role

The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction.

What you'll do

• Define the end-to-end verification strategy, plans, coverage models and signoff criteria
• Architect reusable, scalable SystemVerilog/UVM testbenches and VIP at subsystem and SoC level
• Drive constrained-random, assertion-based (SVA), formal, power-aware (UPF) and gate-level verification
• Establish regression, automation and quality metrics infrastructure
• Lead technical reviews of test plans, testbench architecture and coverage closure

What you need

• 10–18 yrs of experience
• Verilog
• UVM
• Python
• Perl
• Test cases
• VLSI
• Any graduate

Good to have

• FPGA
• Prototyping