Tech Lead ASIC Design Engineer

About the role

As a Lead Digital Design Engineer , you will be responsible for the design and implementation of complex digital IPs and SoC subsystems for next-generation AI infrastructure products. You will drive RTL development from architecture through implementation, collaborate closely with cross-functional teams, and provide technical leadership to ensure high-quality, first-pass silicon.

What you'll do

• Lead the architecture, microarchitecture, RTL design, and implementation of complex digital IPs and SoC subsystems for high-performance connectivity products
• Drive end-to-end ownership of design modules from specification through RTL development, integration, and silicon bring-up
• Design high-quality, synthesizable RTL using Verilog/System Verilog, ensuring optimal performance, power, area (PPA), and scalability
• Develop complex data paths, control logic, finite state machines, arbitration mechanisms, and protocol engines
• Design and implement solutions for high-speed interfaces and protocols, including CXL, PCIe, Ethernet, and AXI-based interconnects

What you need

• 6–12 yrs of experience
• VLSI
• Git
• Python
• Shell scripting
• Verilog
• Perl
• B.Tech or B.E. or M.Tech

Good to have

• Arbitration