Tech Lead, STA

About the role

In this role, you'll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry. This is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity.

What you'll do

• Full-Chip STA Signoff & Timing Closure
• Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs
• Drive timing convergence on advanced process nodes (5nm/4nm/3nm and below) from early floorplan through tapeout
• Analyze and resolve setup, hold, recovery/removal, and clock-domain crossing (CDC) timing violations at the chip level
• Methodology & Flow Development

What you need

• 6–11 yrs of experience
• Python
• VLSI
• Perl
• Root cause analysis
• B.Tech or B.E. or M.Tech