Technical Architect

About the role

Validate power intent correctness including isolation, retention, level shifters, power switches, and always-on logic Debug and resolve low-power violations related to missing/incorrect UPF definitions and design connectivity Document VCLP methodologies and train users on low-power best practices

What you'll do

• Enable and execute UPF-based low-power verification at block and full-chip levels
• Create reference low-power flows and testcases to evaluate tools, PDKs, and EM/LP-related collateral
• Develop and automate VCLP workflows to enhance accuracy and reduce runtime of VCLP signoff. Automation using Python/Perl/Tcl is preferred
• Collaborate with RTL, PD, and Power Architecture teams to close low-power issues
• Prepare low-power signoff reports and maintain VCLP checklists

What you need

• 5–9 yrs of experience
• Any graduate

Good to have

• Python
• Perl