highlisted

Technical Architect

HCLTech·India

Pay not stated10–18 yrsFull-time

Read from the company's own careers page; you apply on their site.

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About the role

We are seeking a Principal / Staff Physical Verification Engineer with 10+ years of experience to drive the full-chip layout verification strategy and manufacturing sign-off for our next-generation, high-performance SoCs.

What you'll do

  • Lead the definition, deployment, and execution of full-chip hierarchical physical verification methodologies (DRC, LVS, ERC, ESD, Antenna, and DFM)
  • Serve as the primary technical interface with leading silicon foundries (e.g., TSMC, Intel, Samsung). Critically evaluate, customize
  • Architect clean database aggregation models. Standardize layout hand-offs between third-party IPs, mixed-signal blocks, digital subsystems
  • Troubleshoot, root-cause, and debug the most complex full-chip structural violations—such as massive LVS text-shorts, complex soft-check loops
  • Establish and enforce strict corporate-wide physical verification waiver policies. Conduct formal layout sign-off reviews and audit block-level violations to minimize…

What you need

  • 10–18 yrs of experience
  • Python
  • VLSI
  • Perl
  • B.Tech or B.E.

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