Technical Architect

About the role

We are seeking a senior Full-Chip EMIR / Power Integrity Engineer to lead the reliability analysis and sign-off closure for our next-generation, large-scale digital ASICs and SoCs. In this high-impact role, you will architect the full-chip Power Distribution Network (PDN), manage top-level bump/pad planning, and execute static and dynamic IR drop and electromigration (EM) analyses.

What you'll do

• Execute and sign off on full-chip and block-level static and dynamic IR drop analysis, power/signal electromigration (EM), and route EMIR
• Enabling ASIC EMIR tools for new process node and latest technology features. Detailed knowledge of EMIR concepts and working of ASIC EMIR tool is a must
• Creating reference flows that act as test vehicles to evaluate tools and EM tech files, PDK collaterals (precisely RV techfiles)
• Develop and automate workflows to enhance the efficiency and accuracy of EM IR analysis. Any automation language is must (Preferably python, perl and tcl)
• Debug and troubleshoot design challenges related to EM IR, providing innovative solutions

What you need

• 10–18 yrs of experience
• Power systems
• Any graduate

Good to have

• Python
• Perl