Technical Architect - RTL Design

About the role

We are seeking a skilled Emulation Engineer with hands-on experience in Synopsys ZeBu Emulation platforms and model development. The engineer will be responsible for building, integrating, and validating emulation models for complex SoC/IP designs, enabling accelerated pre-silicon validation, software bring-up, and hardware-software co-verification activities.

What you'll do

• Develop and maintain ZeBu emulation models for IP, subsystem, and SoC-level designs
• Convert RTL designs into emulation-ready models and optimize them for ZeBu platforms
• Perform design partitioning, synthesis, compilation, and capacity analysis for emulation
• Integrate testbench components, transactors, BFMs, and verification environments into emulation platforms
• Support hardware-software co-verification and early software bring-up activities

What you need

• 7–20 yrs of experience
• Verilog
• Python
• FPGA
• Prototyping
• Linux
• B.Tech or B.E. or M.Tech