Technical Lead I - VLSI

About the role

We are looking for a Lead RTL Design Engineer to drive the architecture, design, and execution of high-performance digital subsystems with a strong focus on PCIe-based designs. This role requires deep expertise in RTL development, protocol understanding, and end-to-end ownership from architecture to validation.

What you'll do

• Own end-to-end RTL design and micro-architecture for PCIe-based subsystems
• Translate system requirements into scalable architecture and RTL implementation
• Design PCIe datapath, control logic, buffering, flow control, and ordering mechanisms
• Develop synthesizable RTL using Verilog
• Lead synthesis, lint, CDC/RDC, timing analysis and closure

What you need

• 8–10 yrs of experience
• VLSI
• FPGA
• Verilog
• Any graduate

Good to have

• Python