Technical Lead- PD-PV,Full Chip PNR

About the role

Lead full-chip netlist integration and readiness, ensuring clean connectivity, logical consistency, constraint alignment, and smooth handoff to implementation and signoff.

What you'll do

• Own top-level netlist assembly and integration checks
• Resolve connectivity, hierarchy, naming, and interface issues
• Validate design collateral, constraints, and implementation readiness
• Coordinate with RTL, synthesis, PnR, STA, DFT, and PV teams
• Automate checks and drive issue closure through release

What you need

• 8–12 yrs of experience
• Python
• Verilog
• Perl
• B.Tech or B.E. or M.Tech