Verification Applications Engineer

About the role

Verification Applications Engineer at Synopsys (incl. Ansys). Support customers using Synopsys verification tools like VCS and Verdi, diagnosing simulation issues, debug challenges, and coverage gaps in their design flows.

What you'll do

• Analyze customer testbenches and design environments to identify root causes of verification failures and propose technical solutions that fit their methodology
• Work on verification challenges involving SystemVerilog, UVM, low power verification, and coverage-driven workflows across diverse customer projects
• Build scripts in Tcl, Python, or Perl to automate workflows, replicate customer issues, or demonstrate best practices
• Guide customers through tape-out cycles, helping them stay on schedule by resolving verification bottlenecks quickly and effectively
• Travel occasionally to customer sites for onsite technical engagements, training, or critical project support

What you need

• 2–5 years in electrical & electronics
• Verilog
• UVM
• Python
• Customer success
• Perl
• Linux
• B.Tech or B.E.