Verification Engineering Lead/Manager

About the role

The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality for mixed signal SOC.

What you'll do

• Lead the SOC and Mixed signal verification team and efforts
• Build capable verification team and manage the tasks and the team to get to tape out on agreed upon schedule and to Production with Agreed upon turns. Revision 0 Silicon…
• Develop and signoff on test plans and test cases
• Develop the Test benchses for AMS and FC simulations
• Develop the tests to get 95+% coverage for the simulations

What you need

• 8–14 yrs of experience
• Verilog
• UVM
• Python
• Test cases
• Perl
• Linux
• B.Sc or M.Sc

Good to have

• C++
• C