Verification Lead (Lead DV)

About the role

You own verification end to end for a first-of-its-kind chiplet. As a founding hire you define the methodology before there's RTL to verify — this role is on the critical path, and getting the coverage strategy and regression infrastructure right early is the single biggest schedule lever we have.

What you'll do

• Stand up regression/CI infrastructure and nightly runs before design hands over first RTL
• Verification of the in-house engines against an algorithmic golden model, with programmable error injection and error-pattern coverage
• Hardware-assisted verification: bring up and own the emulation / FPGA-prototyping methodology
• UCIe VIP and compliance, link-training, loopback, lane-repair scenarios, bit-exact transparency and more
• Performance and throughput verification

What you need

• UVM
• FPGA
• Verilog
• Prototyping
• Any graduate