How to get hired
The roles, in plain words
A chip goes from an idea to silicon through several teams. Pick one to prepare for, because interviews are role-specific.
- RTL design: writing the chip's logic in Verilog or SystemVerilog, micro-architecture, synthesis basics. Fewer fresher openings; strong digital design needed.
- Design verification (DV): proving the design works before it is built, using SystemVerilog testbenches, UVM, assertions and coverage. The largest group of VLSI jobs and the most common fresher entry.
- DFT (design for test): scan insertion, ATPG, memory BIST and boundary scan, so that every manufactured chip can be tested. Titles like "DFT Engineer" appear often in Bengaluru and Hyderabad.
- Physical design (PD): turning the netlist into a layout: floorplan, placement, clock tree synthesis, routing, and static timing analysis (STA) to meet timing. Long tool runs and heavy scripting.
- Analog and mixed-signal: circuit design and layout of ADCs, PLLs, I/Os and memory interfaces. Usually M.Tech-heavy.
- FPGA: design and prototyping on FPGAs, common in defence, telecom and test equipment.
- Post-silicon and validation: testing real chips in labs, often with Python automation.
The three realistic entry routes
- Campus at a strong college: chip companies visit IITs, NITs and leading private colleges for design and verification roles, with written tests on digital electronics and an interview.
- M.Tech in VLSI or microelectronics: the most reliable route for design, analog and PD roles. GATE (EC or EE) is the main gateway to IIT and NIT M.Tech seats.
- Design-services companies: firms that provide verification, DFT and PD engineers to chip companies hire B.Tech freshers in batches, train them and deploy them on client projects. Many people start here and move to a product company after two or three years. Read any service bond carefully; our bond guide explains what is reasonable.
Paid VLSI training institutes
Many private institutes offer four to six months of VLSI training with access to commercial EDA tools, for fees that can run into lakhs. Some place students well; some promise more than they deliver. Before paying, ask for a list of last batch's placements with company names, speak to two past students yourself, and get the refund policy in writing. Also check whether your own college has free tool access and labs through the government's Chips to Startup programme, which has trained tens of thousands of students in VLSI and embedded design.
What VLSI interviews test
- Digital design for everyone: combinational and sequential circuits, FSM design, setup and hold time with a worked timing problem, metastability and clock domain crossing (synchronisers, FIFOs), counters and dividers
- Verilog/SystemVerilog: blocking vs non-blocking, writing a small module live, for DV roles classes, randomisation, constraints, the UVM phases and components
- CMOS basics: inverter characteristics, power, sizing, for PD and analog roles
- Scripting: Perl, Python, TCL or shell to process reports; almost every role uses it Bring a project you can explain: a UART or FIFO you designed and verified with your own testbench, or a small processor on an FPGA board.
What the work is like
Desk work in large offices in Bengaluru, Hyderabad, Noida and a few other cities, with hybrid arrangements at some companies. Work is calm for months and then intense before a tape-out, with late nights and weekend runs. Teams often work with colleagues in the US, Europe or Japan, so expect some evening calls. Growth runs Engineer, Senior, Lead or Staff, Principal; switching companies every few years is common and usually comes with a strong raise for engineers with tape-out experience.