Analog Design, Sr Staff Engineer

About the role

Analog Design, Sr Staff Engineer at Synopsys (incl. Ansys). Design and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs.

What you'll do

• Design and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs
• Run SPICE simulations across PVT corners and create verification test benches that validate performance against PCIe 6.0, PCIe 7.0, PAM4, Ethernet, USB, HDMI
• Collaborate closely with layout engineers to minimize parasitic resistance and capacitance, reduce mismatch
• Work with digital RTL engineers to verify calibration loops, adaptation algorithms, and control logic that tune your analog circuits in real time
• Present simulation results, design tradeoffs, and performance data in peer reviews and customer-facing technical discussions

What you need

• 5–10 yrs of experience
• Circuit design
• Test cases
• Perl
• Calibration
• B.Tech or B.E. or M.Tech or PhD