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ASIC Engineering Digital Design Leader (Digital design, FSM, CPU sub-systems, complex SOCs | 12-16 Years | Pune/ Bangalore)

Cisco·Pune

Pay not stated12–16 yrsFull-time

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About the role

We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability.

What you'll do

  • Lead all design activities from Pre-Silicon RTL to GDS2 signoff and Post-Silicon activities such as FPGA prototyping, Lab Validation and ATE bring-up
  • Lead the architecture and design of complex digital blocks and CPU subsystems. Work seamlessly across cross function teams and resolve design and technical issues
  • Understand and support FW architecture and support FW based verification

What you need

  • 12–16 yrs of experience
  • FPGA
  • Prototyping
  • Any graduate

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