ASIC Physical Verification Lead

About the role

We are looking for an experienced ASIC Physical Verification Lead with around 10 years of experience to drive physical verification signoff activities for complex SoC and IP designs across multiple technology nodes.

What you'll do

• Lead physical verification signoff for ASIC/SoC projects from block level to full-chip tapeout
• Own and drive closure of DRC, LVS, ERC, Antenna, Density, and reliability verification checks
• Debug complex physical verification issues and collaborate with Physical Design, Layout, Circuit Design, and Foundry teams for resolution
• Develop and enhance verification methodologies, automation, and signoff flows
• Mentor junior engineers and lead technical reviews

What you need

• 8–12 yrs of experience
• Inventory counting
• Circuit design
• VLSI
• Python
• Shell scripting
• Perl
• Any graduate