Design Verification Engineer 2

About the role

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Energy feeds on energy.

What you'll do

• Inviting candidates with a passion for invention and self-challenge
• This team will allow you to integrate multiple sophisticated IP level Design and Verification (DV) environments, craft highly reusable best-in-class UVM TB
• Be able to learn all aspects of a FPGA, different types of SOC architecture, many highspeed layered protocols
• This position requires someone comfortable will all areas of FPGA design verification engineering
• Someone that thrives in a dynamic multi-functional organization and is not afraid to take on challenges and solve complex problems using state of the art verification…

What you need

• 3–6 yrs of experience
• UVM
• FPGA
• Verilog
• Test cases
• B.Sc or B.Tech or B.E.