[India] Senior ASIC Implementation Engineer

About the role

We are seeking a highly skilled Senior ASIC Implementation Engineer to join our team. The successful candidate will be responsible for a range of key ASIC implementation tasks, including but not limited to synthesis, timing constraints, implementing ECOs, STA, Power intent implementation & validation, lint, power analysis, CDC RDC Analysis & Validation.

What you'll do

• Professional ASIC hardware design and/or implementation experience
• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
• Debug the timing/area/congestion issues in physical implementation and work with RTL & Physical desig teams to resolve them
• Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities
• Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures

What you need

• 4–7 yrs of experience
• VLSI
• Python
• Perl
• Computer vision
• B.Sc or B.Tech or B.E.

Good to have

• Linux