[India] Senior PCIe Verification Engineer

About the role

We are seeking an experienced Senior PCIe Verification Engineer to join our SoC Verification team. The ideal candidate should have strong expertise in PCI Express (PCIe) IP/Subsystem verification using SystemVerilog/UVM and hands-on experience in 2–3 successful SoC tape-outs. The candidate will be responsible for developing robust verification environments, driving verification closure, and ensuring first-pass silicon success for PCIe-based subsystems.

What you'll do

• Develop and execute comprehensive verification plans for PCIe IPs, subsystems, and SoC integration
• Build reusable SystemVerilog/UVM verification environments from scratch
• Develop constrained-random and directed test scenarios for PCIe verification
• Verify PCIe functionality across LTSSM, Link Training, Configuration Space, Enumeration, Data Link Layer, Transaction Layer, and PHY interactions
• Verify advanced PCIe features such as MSI/MSI-X, AER, ASPM, LTR, SR-IOV, ATS, PASID, FLR, and Power Management (as applicable)

What you need

• 6–12 yrs of experience
• UVM
• Verilog
• VLSI
• Test cases
• Computer vision
• Any graduate