[India] Senior UCIe Verification Engineer

About the role

We are looking for a Senior UCIe Verification Engineer with strong experience in SystemVerilog/UVM-based verification of high-speed interconnects and SoC subsystems. The ideal candidate should have hands-on experience in verifying UCIe (Universal Chiplet Interconnect Express) IP and should have contributed to at least 1–2 successful SoC tape-outs.

What you'll do

• Develop and execute comprehensive verification plans for UCIe IP, subsystems, and SoC integration
• Build reusable SystemVerilog/UVM verification environments from scratch
• Develop constrained-random and directed test scenarios to verify UCIe functionality and protocol compliance
• Link initialization and training
• Data transfer and flow control

What you need

• 6–12 yrs of experience
• UVM
• Verilog
• VLSI
• Test cases
• Computer vision
• Any graduate

Good to have

• Python
• CI/CD
• Jenkins
• Perl
• Git