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Memory Layout Manager

Intel·Bengaluru

Pay not stated15–27 yrsFull-time
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About the role

We are seeking a skilled and motivated Layout Design Engineering Manager to lead a team of layout engineers in delivering best in class SRAM,RF,ROM,CAM Memory compiler designs across the Intel's bleeding FinFETs,GAA technologies.

What you'll do

  • Lead and mentor a team of layout design engineers to developed world class memory compiler designs on FinFets/GAA technologies
  • Oversee the design, development, modification, analysis, and verification of memory compiler layout designs
  • Provide technical guidance for analog, digital, memory, and standard cell layout methodologies, compilers, tools, and flows
  • Enable teams to execute effectively by setting clear objectives, maintaining accountability and facilitating productive workflows through AI-driven EDA tools and…
  • Manage resources effectively to optimize project execution and meet performance targets

What you need

  • 15–27 years in electrical & electronics
  • VLSI
  • Circuit design
  • Machine learning
  • Python
  • B.Tech or B.E.

Good to have

  • Performance management

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Can I apply
Needs B.Tech or B.E. · 20–30 yrs
Pay
Pay not stated
Source
From the company's careers page · today
How to apply
On Altera's site (Workday): account needed, ~10–15 min
Early: posted 2 h ago on their own site