Power Architect – AI SOC

About the role

We are seeking a critical-thinking, highly collaborative Power Architect to drive end-to-end PPA (Power, Performance, Area) excellence for our next-generation AI semiconductor chips. In this cross-functional IC role, you will bridge the gap between front-end conceptualization and back-end implementation, influencing SoC architecture, RTL design, and physical layout to deliver industry-leading power efficiency for complex AI workloads.

What you'll do

• Influence microarchitecture, memory hierarchies, and dataflows to minimize dynamic and leakage power for AI inference and training workloads
• Collaborate directly with Physical Design (PD) teams to refine area constraints, floorplanning, and multi-voltage domain structures
• Develop custom scripts and design workflows where standard tools fall short to squeeze out every milliwatt of power savings
• Cross-Functional Collaboration: Lead PPA analysis and trade-off discussions across RTL, architecture, and PD teams
• Act as the central hub to resolve complex bottlenecks and ensure the final silicon meets strict power budgets

What you need

• 12–22 yrs of experience
• Python
• VLSI
• Verilog
• Perl
• B.Sc or M.Sc or PhD or B.Tech or B.E.