Principal Design Verification Engineer

About the role

The candidate will work as a design verification engineer for wireless communication ASICs development in Pune, India. You will be in the center of the organization impacting and influencing many cross-functional teams.

What you'll do

• Maintain and develop SystemVerilog/UVM methodology test bench within digital IP blocks, including circuit calibration, DSP, CPU subsystems
• Create constrained random stimulus, write checkers and assertions. Analyze simulation results and debug/root cause issues
• Verify power intent through use of methodologies like UPF
• Develop scripts needed to improve efficiency of tasks
• Work closely with digital IP design team to develop comprehensive test strategies to validate use cases

What you need

• 5–9 yrs of experience
• UVM
• Verilog
• Python
• Perl
• Calibration
• B.Tech or B.E.

Good to have

• C++
• C