Principal Verification Engineer

About the role

We are seeking a highly motivated, technically strong, and execution-focused Individual Contributor to lead and deliver first-pass success for complex Digital IP and Subsystem verification programs. The role demands deep expertise in advanced verification methodologies, strong ownership mindset, and ability to collaborate across multi-disciplinary and global teams.

What you'll do

• Lead end-to-end verification execution for complex IPs and Subsystems, ensuring high quality and first-pass silicon success
• Evaluate, adopt, and deploy advanced and scalable verification methodologies to handle increasing design complexity
• Own verification quality metrics across planning, execution, and closure phases
• Drive ‘Zero Defect’ mindset through rigorous process adherence, coverage closure, and defect prevention strategies
• Analyze existing verification flows and implement improvements to enhance efficiency, predictability, and quality

What you need

• 10–15 yrs of experience
• Verilog
• UVM
• C++
• Embedded C
• C
• Any graduate