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Senior Design Engineer(FPGA RTL)

Lattice Semiconductor·Hyderabad

Pay not stated5–9 yrsFull-time

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About the role

We are seeking a Senior IP Design engineer with significant hands-on experience in FPGA RTL design, logic simulation, FPGA compilation and timing closure and hardware debug.

What you need

  • 5–9 yrs of experience
  • FPGA
  • Verilog
  • C++
  • C
  • Python
  • System design
  • B.Sc or M.Sc or PhD or B.Tech or B.E.

Good to have

  • Perl

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