Senior Design Engineer

About the role

You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs. You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.

What you'll do

• Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan)
• Develop and integrate scan insertion, test compression, and ATPG patterns
• Implement memory BIST and logic BIST strategies
• Collaborate with RTL and physical design teams for DFT insertion and timing closure
• Perform DFT verification at RTL and gate-level simulations

What you need

• VLSI
• B.Tech or B.E.