Senior Digital Design Engineer

About the role

We are seeking a highly motivated Synthesis & Front-End Implementation Engineer to join our dynamic team. In this role, you will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.

What you'll do

• Performing synthesis of RTL designs for various digital blocks and sub-systems, including hierarchical synthesis methodologies
• Developing and implementing robust timing constraints (SDC) to achieve target frequencies and optimize design performance
• Conducting STA, identifying critical paths, and collaborating with design teams for timing closure
• Executing formal verification (LEC) to ensure functional equivalency between RTL and synthesized netlists
• Analyzing and optimizing power consumption at the front-end stage, utilizing power analysis tools and techniques

What you need

• 5–9 yrs of experience
• VLSI
• Python
• Verilog
• Perl
• B.Tech or B.E. or M.Tech