Senior Engineer, Post Silicon Validation

About the role

Do you have a passion for invention and self-challenge? This position gives you an opportunity to learn and participate in one of the most cutting-edge projects that Lattice’s Silicon Engineering team has embarked upon to date. various IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc.

What you'll do

• Have an opportunity to learn and train yourself on how to validate one/or many of the building
• Be able to acquire knowledge on process/methodology required for validating certain IPs from
• Be exposed to cutting edge equipment and advanced boards as well as
• Develop validation and characterization plans for certain IP, bench hardware and software
• Develop test logic RTL to achieve intended validation/characterization test

What you need

• 2–5 yrs of experience
• FPGA
• Verilog
• Python
• Test automation
• Perl
• R
• B.Tech or B.E.

Good to have

• Prototyping