Senior Lead Engineer - SoC Design Verification

About the role

We are seeking a highly driven Senior Design Verification Engineer for RTL functional verification of cutting-edge in‑vehicle networking devices within NXP’s next‑generation automotive product line. In this individual‑contributor role, you will architect, enhance, and maintain advanced UVM‑based and C‑based verification environments.

What you'll do

• Create robust verification architecture, verification testplan and verification metric closure documentation to comply with NXP verification and validation process
• Architect and develop testbenches using System Verilog and UVM for functional and power aware RTL verification
• Contribute to defining verification strategy (Directed, Constrained random and Formal) for IP, Sub-System and SoC verification
• Develop UVM components like Agents (active and passive), Scoreboards and Environment etc., Develop Assertions, functional coverage
• Develop Test plan, UVM based test sequences, layered sequences, virtual sequencers

What you need

• 8–14 yrs of experience
• UVM
• Verilog
• C++
• C
• Python
• Circuit design
• Any graduate

Good to have

• JIRA
• Perl
• Git
• Confluence
• FPGA
• Test cases