Senior/Principal verification Engineer

About the role

Define comprehensive verification strategies and verification plans based on architecture and design specifications. Develop and execute block-level, subsystem-level, and SoC-level verification environments. Drive verification closure through functional, code, assertion, and toggle coverage metrics. Create test plans, verification testcases, and sign-off criteria.

What you'll do

• Define comprehensive verification strategies and verification plans based on architecture and design specifications
• Develop and execute block-level, subsystem-level, and SoC-level verification environments
• Drive verification closure through functional, code, assertion, and toggle coverage metrics
• Create test plans, verification testcases, and sign-off criteria
• Architect and develop scalable SystemVerilog/UVM-based verification environments

What you need

• UVM
• Verilog
• Test cases
• Root cause analysis
• Performance testing
• Any graduate