Senior Solution Architect

About the role

We are seeking a highly experienced Clocking/Constraints/STA Lead to join our Physical Design team. In this critical leadership role, you will not only be responsible for your own technical expertise but also for guiding and mentoring a team of engineers to achieve exceptional timing closure for our IC designs.

What you'll do

• Lead the development and implementation of comprehensive clocking strategies for high-performance ICs
• Define and manage timing constraints throughout the design flow, ensuring accurate and consistent timing analysis
• Stay up-to-date with the Perform advanced Static Timing Analysis (STA) using industry-standard tools, identifying potential timing violations and bottlenecks
• Develop and maintain robust clock tree synthesis (CTS) methodologies for optimal clock distribution and skew control
• Drive the creation and execution of a comprehensive clock domain crossing (CDC) verification plan

What you need

• 15–27 yrs of experience
• VLSI
• B.Tech or B.E. or M.Tech