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Sr Principal Product Validation Engineer

Cadence·Noida

Pay not statedLead levelFull-time

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About the role

The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.

What you need

  • Verilog
  • C++
  • UVM
  • Any graduate

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