Staff EDA Engineer

About the role

Qualified candidates must hold a BS or MS degree in EE, ECE, or CoE with 8 to 12 years of industry experience on 5, 7, 16, or 28 nm process technology nodes. This individual will be a key driver in developing, deploying, and supporting the logic and digital design implementation and signoff methodologies and flows across the company's FPGA product lines

What you'll do

• Deploy advanced variation modeling methodologies including AOCV, POCV, and LVF, and define derating and margining strategies across process nodes
• Drive crosstalk and signal integrity analysis, noise-aware timing, and correlation between implementation and signoff timing engines
• Define and automate SDC generation, validation, and equivalence checking across RTL, synthesis, PNR, and signoff stages
• Drive top-level timing closure strategies that rely on abstracted models to reduce runtime and memory footprint on large hierarchical designs
• Drive floorplanning, power planning, placement, clock tree synthesis, and routing methodology, including low-skew and clock mesh structures

What you need

• 8–12 yrs of experience
• VLSI
• FPGA
• M.Sc