RTL Design Architect

About the role

Define micro-architecture and lead RTL design and SoC/subsystem integration for complex silicon, owning PPA and design quality through tape-out.

What you'll do

• Define micro-architecture, block partitioning and interface specifications from system requirements
• Own PPA trade-offs and RTL quality: lint, CDC/RDC, synthesis and constraints (SDC, UPF)
• Lead subsystem and SoC integration, and drive design and code reviews
• Partner with DV, DFT and PD to close verification, testability, timing and power
• Mentor and technically guide RTL teams; act as the escalation point for design issues

What you need

• 15–27 yrs of experience
• Verilog
• Python
• Perl
• Root cause analysis
• FPGA
• Prototyping
• Any graduate

Good to have

• Performance testing
• Roadmapping
• Branding