ASIC Digital Design, Staff Engineer-17879

About the role

ASIC Digital Design, Staff Engineer-17879 at Synopsys (incl. Ansys). Architect and implement RTL designs for high-performance IP cores focused on die-to-die communication protocols including UCIe.

What you'll do

• Architect and implement RTL designs for high-performance IP cores focused on die-to-die communication protocols including UCIe
• Write micro-architecture documents that translate functional specifications into implementable design solutions for complex digital components, defining data paths
• Own the full design flow from RTL coding in SystemVerilog through synthesis, CDC analysis, formal verification, and static timing closure using tools like Fusion Compiler
• Collaborate directly with the verification team to define testplans, close coverage gaps, and debug corner cases that surface during regression or customer testing
• Interface with customers to clarify specification ambiguities, align on design intent, and ensure the IP meets real-world integration requirements

What you need

• 12–22 yrs of experience
• Verilog
• VLSI
• Perl
• Any graduate