Principal Analog Design Engineer

About the role

We are seeking an experienced Analog Design Engineer with 12-18 years of expertise in high-performance PLL and clocking solutions to join our product development team. The candidate will lead the design and development of advanced clock generation, distribution, synchronization, and timing circuits for next-generation SoCs and mixed-signal products, driving innovations from architecture definition through silicon validation and production.

What you'll do

• Architect, design, and verify high-performance PLL, clock generation, clock distribution, and synchronization circuits for advanced semiconductor products
• Own end-to-end analog design execution including specification definition, transistor-level implementation, performance verification, and silicon bring-up
• Develop innovative analog circuit solutions to optimize jitter, phase noise, power consumption, and overall system performance
• Work closely with system, digital, layout, validation, and product engineering teams to define interfaces, calibration methodologies, and verification strategies
• Drive reliability, EMC/ESD compliance, silicon characterization, and yield improvement activities

What you need

• 12–22 yrs of experience
• Circuit design
• Calibration
• Any graduate