Staff/ Sr Staff Engineer, Physical Design

About the role

We are seeking an experienced Physical Design Engineer with strong debug skills in Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on RTL synthesis ownership, LEC closure, UPF development, and VCLP sign‑off for complex SoC designs, working closely with Physical Design, DFT, and Front‑End teams.

What you'll do

• Own RTL synthesis from elaboration to final sign‑off
• Develop and debug design constraints and support DFT insertion
• Understand Physical design cycle and different handshaking across teams
• Perform and close logic equivalence checks (LEC) across RTL, synthesized, and ECO netlists
• Create, maintain, and debug UPF, ensuring alignment with FE power intent

What you need

• 7–10 yrs of experience
• VLSI
• Any graduate

Good to have

• Python
• Perl